SIGMA ISA
Open-source 128-bit RISC processor architecture with custom microarchitecture and operating system
Project Overview
SIGMA (Scalable Integrated General-purpose computing Machine Architecture) is a comprehensive computing platform built from the ground up, including a custom 128-bit RISC instruction set architecture, microarchitecture design, system-on-chip specification, and a Linux-based operating system.
Created collaboratively with three other architects, SIGMA addresses fundamental limitations in existing processor architectures. While ARM and x86 dominate the market with proprietary licenses and legacy compatibility baggage, and RISC-V remains incomplete with unratified memory models and missing SIMD support, SIGMA provides a clean, modern, fully open-source alternative designed for high-performance computing from the start.
The project encompasses the complete computing stack: from the ISA specification with 32 general-purpose registers and quad-precision floating point support, to the Electron microarchitecture with simultaneous multithreading, to the North Star SOC with PCIe 4.0 and DDR5 support, to the Nebula operating system with a ported GCC compiler and custom package manager.
The Architecture
SIGMA represents a ground-up redesign of processor architecture with modern requirements in mind:
128-bit Word Size: Native 128-bit operations with support for 8, 32, 64, and 128-bit data formats
32 General Purpose Registers: Each 128 bits wide for high-performance computation
Advanced Floating Point: Up to IEEE quad-precision (128-bit) floating point, plus BFloat16 and TensorFloat formats for ML workloads
SIMD Extensions: 32 dedicated 256-bit SIMD registers for parallel data processing
Vector Processing: Full vector instruction support for high-throughput computing
RISC Philosophy: Clean, simple instruction set without legacy compatibility modes that plague x86
The architecture is completely open-source and free to implement, avoiding the licensing restrictions of ARM and x86 that limit academic and commercial innovation.
Electron Microarchitecture
The Electron microarchitecture implements the SIGMA ISA with aggressive performance optimizations:
Deep Pipeline: 10-stage pipeline with 6 decode stages for complex instruction handling
Execution Units: 6-10 ALUs for high instruction throughput
Simultaneous Multithreading: Hardware-level thread scheduling for improved utilization
Specialized Processing: 2-4 dedicated floating-point units and 2-4 SIMD units
Modern Memory Hierarchy: 512KB L1 cache, 10MB total L2 cache
The microarchitecture design prioritizes both single-thread performance and parallel workload efficiency, making it suitable for applications ranging from general-purpose computing to scientific computing and machine learning.
North Star SOC & Nebula OS
The complete platform includes system-level integration:
North Star System-on-Chip:
30 PCIe 4.0 lanes for high-bandwidth peripheral connectivity
20 USB 4 lanes for modern device support
DDR5 memory controller for cutting-edge memory performance
Direct VRAM interface for GPU acceleration
Advanced cache hierarchy for reduced memory latency
Nebula Operating System:
Linux-based foundation for compatibility and stability
Ported GCC compiler for immediate software ecosystem support
Custom package manager optimized for the platform
ZSH shell with modern command-line tools
Clean, personalized UI built from scratch
The OS layer ensures that SIGMA isn't just a theoretical design - it's a fully functional computing platform ready for software development.
Why Build a New ISA?
The motivation for SIGMA stems from fundamental issues in the current processor landscape:
Legacy Burden: x86 carries decades of backwards compatibility, inflating die sizes and power consumption with rarely-used instructions
Licensing Restrictions: ARM and x86 require expensive licenses that restrict academic research and commercial innovation
Incomplete Alternatives: RISC-V, while open-source, was designed for education rather than commercial deployment and lacks critical features like a ratified memory model and standard SIMD instructions
Modern Requirements: Machine learning, scientific computing, and data processing demand native support for wide data types and parallel execution
SIGMA addresses all these issues with a clean, modern design that's both legally open and technically complete. The 128-bit architecture provides native support for emerging workloads while maintaining the simplicity and efficiency of RISC principles.
Built collaboratively by four architects, SIGMA demonstrates that competitive processor designs don't require billion-dollar corporations - just deep understanding of computer architecture and willingness to challenge established designs.
Skills & Technologies
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Project Info
November 2023 - December 2023
Completed